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Ordering number : ENA0664
LC87F5LP6A
Overview
CMOS IC FROM 256K byte, RAM 8192 byte on-chip
8-bit 1-chip Microcontroller
The SANYO LC87F5LP6A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrate on a single chip a number of hardware features such as 256K-byte flash ROM (onboard rewritable), 8K-byte RAM, Onchip debugging function, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 15-channel AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt feature.
Features
Flash ROM * Single 5V power supply, on-board writeable * Block erase in 128 byte units * 262144 x 8 bits (LC87F5LP6A) RAM * 8192 x 9 bits (LC87F5LP6A) Minimum Bus Cycle Time * 83.3ns (12MHz) Note: Bus cycle time indicates the speed to read ROM. Minimum Instruction Cycle Time (tCYC) * 250ns (12MHz)
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.1.01
31407HKIM 20061227-S00001 No. A0664-1/28
LC87F5LP6A
Ports * Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units Ports whose I/O direction can be designated in 2-bit units Ports whose I/O direction can be designated in 4-bit units * Normal withstand voltage input port * Dedicated oscillator ports * Reset pin * Power pins
64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn, S2Pn, PWM0, PWM1, XT2) 16 (PEn, PFn) 8 (P0n) 1 (XT1) 2 (CF1, CF2) 1 (RES) 8 (VSS1 to VSS4, VDD1 to VDD4)
Timers * Timer 0: 16-bit timer/counter with capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) x2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with 216-bit capture registers) * Timer 1: 16-bit timer/counter that support PWM/ toggle output Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) * Timer 4: 8-bit timer with a 6-bit prescaler * Timer 5: 8-bit timer with a 6-bit prescaler * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillator), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes. High-speed Clock Counter 1. Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2. Can generate output real-time. 3. Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz). SIO * SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits) * SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) * SIO2: 8 bit synchronous serial interface 1) LSB first mode 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 32 bytes)
No.A0664-2/28
LC87F5LP6A
UART: 2 channels 1) Full duplex 2) 7/8/9 bit data bits selectable 3) 1 stop bit (2 bits in continuous transmission mode) 4) Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC) AD Converter * 8 bits x 15 channels PWM * Multifrequency 12-bit PWM x 4 channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) 1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) 2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. Watchdog Timer 1) External RC watchdog timer 2) Interrupt and reset signals selectable Interrupts * 29 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/INT5/base timer T0H/INT6 T1L/T1H/INT7 SIO0/UART1 receive/ UART2 receive SIO1/SIO2/UART1 transmit/UART2 transmit ADC/T6/T7/PWM4, PWM5 Port 0/T4/T5/PWM0, PWM1 Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels * 4096 levels maximum (the stack is allocated in RAM) High-speed Multiplication/Division Instructions * 16-bits x 8-bits (5 tCYC execution time) * 24-bits x 16-bits (12 tCYC execution time) * 16-bits / 8-bits (8 tCYC execution time) * 24-bits / 16-bits (12 tCYC execution time) Oscillation Circuits * RC oscillation circuit (internal) * CF oscillation circuit * Crystal oscillation circuit * Multifrequency RC oscillation circuit (internal)
: For system clock : For system clock, with internal Rf : For low-speed system clock : For system clock
No.A0664-3/28
LC87F5LP6A
System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). * The minimum instruction cycle selectable from 250ns, 500ns, 1.0s, 2.0s, 4.0s, 8.0s, 16.0s, 32.0s, and 64.0s (at a main clock rate of 12MHz). Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of interrupt. * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit On-chip Debugger Function * Permits software debugging with the test device installed on the target board. Package Form * QIP100E (14 x 20) : "Lead-free type" * TQFP100 (14 x 14) : "Lead-free type" Development Tools * Evaluation (EVA) chip * Emulator
: LC87EV690 : EVA62S + ECB876600D + SUB875C00 + POD100QFP or POD100SQFP Type B ICE-B877300 + SUB875C00 + POD100QFP or POD100SQFP Type B * Flash ROM writer adapter : W87F52256Q(QIP100E), W87F52256SQ(TQFP100)
No.A0664-4/28
LC87F5LP6A
Package Dimensions
unit : mm (typ) 3151A
23.2 80 81 51 50
0.8 14.0
20.0
100 1 0.65 (0.58)
(2.7)
31 30 0.3 0.15
3.0max
0.1
SANYO : QIP100E(14X20)
Package Dimensions
unit : mm (typ) 3274
16.0 14.0 75 76 51 50
17.2
0.5
100 1 (1.0)
(1.0)
26 0.5 0.2 25 0.125
1.2max
0.1
SANYO : TQFP100(14X14)
14.0 16.0
No.A0664-5/28
Pin Assignments
PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7/DBGP2 PC6/DBGP1 PC5/DBGP0 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
LC87F5LP6A
LC87F5LP6A
PA3/AN12 PA4/AN13 PA5/AN14 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
PB7 P36 P35/URX2 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1 P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P21/INT4/T1IN/T0LCP/T0HCP P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1 P07/T7O P06/T6O P05/CKO P04 P03 P02 P01 P00 VSS2 VDD2 PWM0 PWM1 SI2P3/SCK20 SI2P2/SCK2
Top view
SANYO: QIP100E(14x20) "Lead-free Type"
No.A0664-6/28
SI2P1/SI2/SB2 SI2P0/SO2 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 VDD4 VSS4 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
LC87F5LP6A
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P36 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7/DBGP2 PC6/DBGP1 PC5/DBGP0 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 PA3/AN12 PA4/AN13 PA5/AN14 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PWM1 SI2P3/SCK20 SI2P2/SCK2 SI2P1/SI2/SB2 SI2P0/SO2 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 VDD4 VSS4 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 P17/T1PWMH/BUZ P16/T1PWML
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1
P35/URX1 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/ T0LCP/T0HCP P26/INT5/T1IN/ T0LCP/T0HCP P25/INT5/T1IN/ T0LCP/T0HCP P24/INT5/T1IN/ T0LCP/T0HCP/INT7/T0HCP1 P23/INT4/T1IN/ T0LCP/T0HCP P22/INT4/T1IN/ T0LCP/T0HCP P21/INT4/T1IN/ T0LCP/T0HCP P20/INT4/T1IN/ T0LCP/T0HCP/INT6/T0LCP1 P07/T7O P06/T6O P05/CKO P04 P03 P02 P01 P00 VSS2 VDD2 PWM0
LC87F5LP6A
Top view
SANYO: TQFP100(14x14) "Lead-free Type"
No.A0664-7/28
LC87F5LP6A
QIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME PA3/AN12 PA4/AN13 PA5/AN14 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VSS4 VDD4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 SI2P0/SO2 SI2P1/SI2/SB2 TQFP 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 QIP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME SI2P2/SCK2 SI2P3/SCK20 PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05/CKO P06/T6O P07/T7O P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1 P21/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P23/INT4/T1IN/T0LCP/T0HCP P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1 P25/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P27/INT5/T1IN/T0LCP/T0HCP P30/PWM4 P31/PWM5 P32/UTX1 P33/URX1 P34/UTX2 P35/URX2 P36 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7/DBGP2 PC6/DBGP1 PC5/DBGP0 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 TQFP 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
No.A0664-8/28
LC87F5LP6A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM Standby control CF RC X'tal MRC SIO0 Bus interface ACC B register Clock generator PC
SIO1 SIO2
Port 0
Port 1
C register
Timer 0
Port 3 ALU
Timer 1
Port 7
Timer 4
Port 8
PSW
Timer 5
ADC INT0 to 3 Noise rejection filter Port 2 INT4, 5, 6, 7
RAR
PWM0
RAM
PWM1
Stack pointer Base timer Port A Watchdog timer Timer 6 Port B On-chip debugger Timer 7 Port C
UART1
Port E
UART2
Port F
PWM5
PWM4
No.A0664-9/28
LC87F5LP6A
Pin Description
Pin Name VSS1, VSS2 VSS3, VSS4 VDD1, VDD2 VDD3, VDD4 Port 0 P00 to P07 I/O I/O - Power supply pin + Power supply pin * 8-bit I/O port * I/O specifiable in 4-bit units * Pull-up resistor can be turned on and off in 4-bit units * HOLD release input * Port 0 interrupt input * Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output Port 1 P10 to P17 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P10: SIO0 data output P11: SIO0 data input, bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input, bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output, Beeper output Port 2 P20 to P27 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Other functions P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT6 input/timer 0L capture 1 input P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT7 input/timer 0H capture 1 input P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input Interrupt acknowledge type * Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising/ Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Yes Description Option No No Yes
Port 3 P30 to P36
I/O
* 7-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P30: PWM4 output P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit P35: UART2 receive
Yes
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No.A0664-10/28
LC87F5LP6A
Continued from preceding page.
Pin Name Port 7 P70 to P73 I/O I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Other functions P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer P71: INT1 input/HOLD release input/Timer 0H capture input P72: INT2 input/HOLD release input/Timer 0 event input/Timer 0L capture input P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input * Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Description Option No
* AD converter input port: AN8 (P70), AN9 (P71) Port 8 P80 to P87 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Other functions P80 to P87: AD converter input port Port A PA0 to PA5 Port B PB0 to PB7 Port C PC0 to PC7 I/O I/O I/O * 6-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions PC5 to PC7: On-chip Debugger Port E PE0 - PE7 Port F PF0 to PF7 SIO2 Port SI2P0 to SI2P3 I/O I/O I/O * 8-bit I/O port * I/O specifiable in 2-bit units * Pull-up resistor can be turned on and off in 1-bit units * 8-bit I/O port * I/O specifiable in 2-bit units * Pull-up resistor can be turned on and off in 1-bit units * 4-bit I/O port * I/O specifiable in 1-bit units * Shared functions: SI2P0: SIO2 data output SI2P1: SIO2 data input, bus input/output SI2P2: SIO2 clock input/output SI2P3: SIO2 clock output PWM0 PWM1 RES XT1 O O I I * PWM0 output port * General-purpose I/O available * PWM1 output port * General-purpose I/O available Reset pin * Input terminal for 32.768kHz X'tal oscillation * Shared functions: AN10: AD converter input port General-purpose input port Must be connected to VDD1 if not to be used. XT2 I/O * Output terminal for 32.768kHz X'tal oscillation * Shared functions: AN11: AD converter input port General-purpose I/O port Must be set for oscillation and kept open if not to be used. CF1 CF2 I O Ceramic resonator input pin Ceramic resonator output pin No No No No No No No No No No Yes Yes Yes No
No.A0664-11/28
LC87F5LP6A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port P00 to P07 Options Selected in Units of 1 bit Option Type 1 2 P10 to P17 P20 to P27 P30 to P36 PA0 to PA5 PB0 to PB7 PC0 to PC7 PE0 to PE7 PF0 to PF7 P70 P71 to P73 P80 to P87 SI2P0, SI2P2 SI2P3 PWM0, PWM1 SI2P1 No CMOS (when selected as ordinary port) N-channel open drain (When SIO2 data is selected) XT1 XT2 No No Input only Output for 32.768kHz quartz oscillator N-channel open drain (when in generalpurpose No output mode) No No No No No No No N-channel open drain CMOS N-channel open drain CMOS Programmable Programmable No No No CMOS Programmable 1 bit 1 2 CMOS N-channel open drain Programmable Programmable 1 bit 1 2 CMOS N-channel open drain CMOS N-channel open drain Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07). *1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins. (Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the backup capacitors.
Back-up capacitor Power Supply LSI VDD1
VDD2
VDD3
VDD4 VSS1 VSS2 VSS3 VSS4
No.A0664-12/28
LC87F5LP6A
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up capacitor Power Supply
LSI VDD1
VDD2
VDD3
VDD4 VSS1 VSS2 VSS3 VSS4
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Maximum supply voltage Input voltage Input/Output voltage VI(1) VIO(1) Symbol VDD max Pins/Remarks VDD1, VDD2, VDD3, VDD4 XT1, CF1 Ports 0, 1, 2 Ports 3, 7, 8 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1, XT2 Peak output current IOPH(2) IOPH(3) Average output current (Note1-1) High level output current IOM(2) IOM(3) Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOM(1) IOPH(1) Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 P71 to P73 Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 P71 to P73 P71 to P73 PWM0, PWM1 SI2P0 to SI2P3 Ports 0, 2, 3 Ports 0, 2, 3 PWM0, PWM1 SI2P0 to SI2P3 IOAH(5) IOAH(6) IOAH(7) IOAH(8) IOAH(9) IOAH(10) Port B Ports A, C Ports A, B, C Port F Ports 1, E Ports 1, E, F Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins -20 -20 -40 -20 -20 -40 Total of all applicable pins Total of all applicable pins -50 Per 1 application pin. Per 1 application pin. Total of all applicable pins Total of all applicable pins -15 -3 -10 -20 -30 mA Per 1 application pin. Per 1 application pin. CMOS output select per 1 application pin -7.5 -20 -5 CMOS output select per 1 application pin -10 -0.3 VDD+0.3 V Conditions VDD[V] VDD1=VDD2 =VDD3=VDD4 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 unit
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A0664-13/28
LC87F5LP6A
Continued from preceding page.
Parameter Peak output current Symbol IOPL(1) Pins/Remarks P02 to P07 Ports 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 IOPL(2) IOPL(3) Average output current (Note1-1) IOML(1) P00, P01 Ports 7, 8, XT2 P02 to P07 Ports 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 Low level output current IOML(2) IOML(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) P00, P01 Ports 7, 8, XT2 Port 7, XT2 Port 8 Ports 7, 8, XT2 PWM0, PWM1 SI2P0 to SI2P3 Ports 0, 2, 3 Ports 0, 2, 3 PWM0, PWM1 SI2P0 to SI2P3 IOAL(7) IOAL(8) IOAL(9) IOAL(10) IOAL(11) IOAL(12) Maximum power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr Pd max Port B Ports A, C Ports A, B, C Port F Ports 1, E Ports 1, E, F QIP100E(14x20) TQFP100(14x14) -20 -55 Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins 40 40 80 40 70 110 523 364 +70 C +125 mW Total of all applicable pins Total of all applicable pins 120 Per 1 application pin. Per 1 application pin. Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins 20 7.5 15 15 20 40 80 mA 15 Per 1 application pin. Per 1 application pin. Per 1 application pin. 30 10 20 Conditions VDD[V] Per 1 application pin. min Specification typ max unit
Note 1-1: Average output current is average of current in 100ms interval.
No.A0664-14/28
LC87F5LP6A
Recommended Operating Range at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Operating supply voltage (Note2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports 1, 2, 3 SI2P0 to SI2P3 P71 to P73 P70 port input/ interrupt side VIH(2) Ports 0, 8 Ports A, B, C, E, F PWM0, PWM1 VIH(3) VIH(4) Low level input voltage VIL(1) P70 Watchdog timer side XT1, XT2, CF1, RES Ports 1, 2, 3 SI2P0 to SI2P3 P71 to P73 P70 port input/ interrupt VIL(2) Ports 0, 8 Ports A, B, C, E, F PWM0, PWM1 VIL(5) VIL(6) Instruction cycle time tCYC (Note2-2) Port 70 Watchdog timer XT1, XT2, CF1, RES 2.5 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 External system clock frequency FEXCF(1) CF1 * CF2 pin open * System clock frequency division rate=1/1 * External system clock duty=505% * CF2 pin open * System clock frequency division rate=1/2 Oscillation frequency range (Note2-3) FmCF(3) FmCF(4) FmRC FmMRC FsX'tal XT1, XT2 CF1, CF2 CF1, CF2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 10MHz ceramic oscillation See Fig. 1. 8MHz ceramic oscillation See Fig. 1. 4MHz ceramic oscillation See Fig. 1. 12MHz ceramic oscillation See Fig. 1. Internal RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal oscillation. See Fig. 2. 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3 0.1 0.2 0.2 0.2 10 8 5 12 1.0 16 32.768 kHz 2.0 5 24.4 16 10 MHz 3.0 to 5.5 0.1 8 4.5 to 5.5 VSS VSS 0.245 0.367 0.588 0.1 2.5 to 5.5 VSS 0.15VDD +0.4 0.8VDD -1.0 0.25VDD 200 200 200 12 s 2.5 to 5.5 VSS 0.1VDD +0.4 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3VDD +0.7 0.9VDD 0.75VDD VDD V 2.5 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2 =VDD3=VDD4 Symbol VDD(1) Pins/Remarks VDD1=VDD2 =VDD3=VDD4 Conditions VDD[V] 0.245s tCYC200s 0.367s tCYC200s 0.588s tCYC200s RAM and register contents in HOLD mode. 2.0 5.5 min 4.5 3.0 2.5 Specification typ max 5.5 5.5 5.5 unit
VDD VDD
MHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0664-15/28
LC87F5LP6A
Electrical Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4= 0V
Parameter High level input current Symbol IIH(1) Pins/Remarks Ports 0, 1, 2 Ports 3, 7, 8 Ports A, B, C SI2P0 to SI2P3 RES PWM0, PWM1 IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 Using as an input port VIN=VDD CF1 Ports 0, 1, 2 Ports 3, 7, 8 Ports A, B, C, E, F SI2P0 to SI2P3 RES PWM0, PWM1 IIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistation Rpu(1) Rpu(2) Hysteresis voltage VHYS Ports 0, 1, 2, 3 Port 7 Ports A, B, C, E, F RES Ports 1, 2, 7 SI2P0 to SI2P3 Pin capacitance CP All pins * For pins other than that under test: VIN=VSS * f=1MHz * Ta=25C 2.5 to 5.5 10 pF 2.5to 5.5 0.1VDD V 4.5 to 5.5 15 35 120 Ports 7, 8, XT2 Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1, P00, P01 PWM0, PWM1 P30, P31(PWM4, 5 output mode) IOH=-1.6mA IOH=-1.0mA IOL=10mA IOL=1.6mA IOL=1.0mA IOL=30mA IOL=5.0mA IOL=2.5mA IOL=1.6mA IOL=1.0mA VOH=0.9VDD Ports 71, 72, 73 XT1, XT2 Using as an input port VIN=VSS CF1 Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA VIN=VSS IOH=-1.0mA IOH=-0.4mA 2.5 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 15 35 -1 -15 VDD-1 VDD -0.4 VDD -0.4 VDD -0.4 VDD -0.4 VDD -1.5 VDD -0.4 VDD -0.4 1.5 0.4 0.4 1.5 0.4 0.4 0.4 0.4 80 k V VIN=VDD Output disable Pull-up resistor OFF VIN=VSS (including the off-leak current of the output Tr.) 2.5 to 5.5 -1 2.5 to 5.5 2.5 to 5.5 1 15 A Conditions VDD[V] Output disable Pull-up resistor OFF VIN=VDD (including the off-leak current of the output Tr.) 2.5 to 5.5 1 min Specification typ max unit
No.A0664-16/28
LC87F5LP6A
Serial I/O Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level pulse width High level pulse width Input clock tSCKHA(1a) * Continuous data transmission/reception mode * SIO2 is not in use simultaneous. * See Fig. 6. * (Note 4-1-2) tSCKHA(1b) * Continuous data transmission/reception mode * SIO2 is in use simultaneous. Serial clock * See Fig. 6. * (Note 4-1-2) Frequency Low level pulse width High level pulse width Output clock tSCKHA(2a) * Continuous data transmission/reception mode * SIO2 is not in use simultaneous. * CMOS output selected. * See Fig. 6. tSCKHA(2b) * Continuous data transmission/reception mode * SIO2 is in use simultaneous. * CMOS output selected. * See Fig. 6. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold time thDI(1) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.5 to 5.5 0.03 Output Input clock delay time tdD0(2) tdD0(1) SO0(P10), SB0(P11), * Continuous data transmission/reception mode * (Note 4-1-3) * Synchronous 8-bit mode. * (Note 4-1-3) tdD0(3) Output clock * (Note 4-1-3) 2.5 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) +(16/3) tCYC 2.5 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected. * See Fig. 6. 4/3 1/2 tSCK 1/2 6 2.5 to 5.5 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pins /Remarks SCK0(P12) * See Fig. 6. Conditions VDD[V] min 2 1 1 Specification typ max unit
tCYC
(1/3)tCYC +0.05 s 1tCYC +0.05
Serial output
(1/3)tCYC +0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.
No.A0664-17/28
LC87F5LP6A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SI1(P14), SB1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.5 to 5.5 0.03 Output delay Serial output time tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.5 to 5.5 (1/3)tCYC +0.05 s 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected. * See Fig. 6. 2.5 to 5.5 tSCKH(3) Symbol Tsck(3) tSCKL(3) Pins/ Remarks SCK1(P15) * See Fig. 6. Conditions VDD[V] min 2 2.5 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Serial clock
No.A0664-18/28
LC87F5LP6A
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter Frequency Low level pulse width High level pulse width Input clock tSCKHA(5a) * Continuous data transmission/ reception mode of SIO0 is not in use simultaneous. * See Fig. 6. * (Note 4-3-2) tSCKHA(5b) * Continuous data transmission/ reception mode of SIO0 is in use simultaneous. Serial clock * See Fig. 6. * (Note 4-3-2) Frequency Low level pulse width High level pulse width Output clock tSCKHA(6a) * Continuous data transmission/ reception mode of SIO0 is not in use simultaneous. * CMOS output selected. * See Fig. 6. tSCKHA(6b) * Continuous data transmission/ reception mode of SIO0 is in use simultaneous. * CMOS output selected. * See Fig. 6. Data setup time Serial input tsDI(3) SI2(SI2P1), SB2(SI2P1) Data hold time thDI(3) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.5 to 5.5 0.03 Output delay Serial output time tdD0(5) SO2 (SI2P0), SB2(SI2P1) * Must be specified with respect to falling edge of SIOCLK * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.5 to 5.5 (1/3)tCYC +0.05 s 0.03 tSCKH(6) +(5/3)tCYC tSCKH(6) +(19/3)tCYC 2.5 to 5.5 tSCKH(6) +(5/3)tCYC tSCKH(6) +(10/3)tCYC tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK2 (SI2P2), SCK2O (SI2P3) * CMOS output selected. * See Fig. 6. 4/3 1/2 tSCK 1/2 7 2.5 to 5.5 4 tSCKH(5) Symbol tSCK(5) tSCKL(5) Pins/ Remarks SCK2 (SI2P2) * See Fig. 6. Conditions VDD[V] min. 2 1 1 Specification typ max. unit
tCYC
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
No.A0664-19/28
LC87F5LP6A
Pulse Input Conditions at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins/Remarks INT0(P70), INT1(P71), INT2(P72) INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1. INT3(P73) (The noise rejection clock is selected to 1/32.) INT3(P73) (The noise rejection clock is selected to 1/128.) RES Reset acceptable 2.5 to 5.5 200 s * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. 2.5 to 5.5 256 * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. 2.5 to 5.5 64 2.5 to 5.5 2 tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 or 1 are enabled. 2.5 to 5.5 1 min Specification typ max unit
AD Converter Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4= 0V
Parameter Resolution Absolute precision Conversion time TCAD Symbol N ET Pins/Remarks AN0(P80) to AN7(P87), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2), AN12(PA3), AN13(PA4), AN14(PA5) AD conversion time=64xtCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 3.0 to 5.5 AD conversion time=32xtCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 11.74 (tCYC= 0.367s) 31.36 (tCYC= 0.980s) 18.82 (tCYC= 0.294s) 31.36 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0.490s) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 1.5 97.92 (tCYC= 3.06s) 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) 97.92 (tCYC= 1.53s) VDD 1 V s max unit bit LSB
A
Note 6-1: The quantization error (1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0664-20/28
LC87F5LP6A
Consumption Current Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) Pins/Remarks VDD1 =VDD2 =VDD3 =VDD4 Conditions VDD[V] * FmCF=10MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 10MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDOP(2) * FmCF=8MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 8MHz side IDDOP(3) * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDOP(4) * FmCF=5MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode IDDOP(5) * System clock set to 5MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDOP(6) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode IDDOP(7) * System clock set to internal RC oscillation * frequency variable RC oscillation stopped *1/2 frequency division ratio. IDDOP(8) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. * System clock set to 1MHz with frequency IDDOP(9) variable RC oscillation * Internal RC oscillation stopped * 1/2 frequency division ratio. IDDOP(10) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. IDDOP(11) * System clock set to 32.768kHz side. * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/2 frequency division ratio. IDDOP(12) * FmCF=12MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 12MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. HALT mode consumption current (Note 7-1) IDDHALT(1) VDD1 =VDD2 =VDD3 =VDD4 * HALT mode * FmCF=10MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 10MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. 4.5 to 5.5 4 8.5 mA 4.5 to 5.5 10.2 25 2.5 to 4.5 22 85 A 4.5 to 5.5 45 130 2.5 to 4.5 1 6 4.5 to 5.5 1.5 10 2.5 to 4.5 0.7 4 4.5 to 5.5 1.2 6 2.5 to 4.5 3 8.5 4.5 to 5.5 5.5 12 mA 3.0 to 4.5 4.2 12.5 4.5 to 5.5 8 17 4.5 to 5.5 9 22 min Specification typ max unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors
Continued on next page.
No.A0664-21/28
LC87F5LP6A
Continued from preceding page.
Parameter HALT mode consumption current (Note 7-1) IDDHALT(3) Symbol IDDHALT(2) Pins/Remarks VDD1 =VDD2 =VDD3 =VDD4 * HALT mode * FmCF=8MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 8MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDHALT(4) * HALT mode * FmCF=5MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode IDDHALT(5) * System clock set to 5MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDHALT(6) * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode IDDHALT(7) * System clock set to internal RC oscillation * frequency variable RC oscillation stopped *1/2 frequency division ratio. IDDHALT(8) * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. IDDHALT(9) * System clock set to 1MHz with frequency variable RC oscillation * Internal RC oscillation stopped * 1/2 frequency division ratio. IDDHALT(10) * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. IDDHALT(11) * System clock set to 32.768kHz side. * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/2 frequency division ratio. IDDHALT(12) * HALT mode * FmCF=12MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 12MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(4) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD1 * HOLD mode * CF1=VDD or open (External clock mode) 2.5 to 4.5 * Timer HOLD mode * CF1=VDD or open (External clock mode) * FmX'tal=32.768kHz by crystal oscillation mode 4.5 to 5.5 2.5 to 4.5 0.03 19 6.5 17 65 55 A 4.5 to 5.5 0.07 20 4.5 to 5.5 4.7 10 mA 2.5 to 4.5 10 65 4.5 to 5.5 22 75 A 2.5 to 4.5 0.8 3 4.5 to 5.5 1.5 4 2.5 to 4.5 0.25 1 4.5 to 5.5 0.45 1.5 2.5 to 4.5 1 2.8 mA 4.5 to 5.5 2.2 4.5 3.0 to 4.5 1.8 3.2 4.5 to 5.5 3 6 Conditions VDD[V] min Specification typ max unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors
No.A0664-22/28
LC87F5LP6A
F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Onboard programming current Programming time tFW(1) * 128-byte programming * Erasing current including * Time for setting up 128 byte data is excluded. 3.0 to 5.5 22.5 35 ms Symbol IDDFW(1) Pins/Remarks VDD1 Conditions VDD[V] * 128-byte programming * Erasing current including 3.0 to 5.5 30 50 mA min Specification typ max unit
UART (Full Duplex) Operating Conditions at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4= 0V
Parameter Transfer rate Symbol UBR, UBR2 Pins/Remarks UTX1(P32), RTX1(P33), UTX2(P33), RTX2(P34) 2.5 to 5.5 16/3 8192/3 tCYC Conditions VDD[V] min Specification typ max unit
Data length : 7/8/9 bits (LSB first) Stop bits : 1-bit (2-bit in continuous data transmission) Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission
UBR, UBR2
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Start bit Start of reception Receive data (LSB first) Stop bit End of reception
UBR, UBR2
No.A0664-23/28
LC87F5LP6A
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below. * Place capacitors as close to VDD1 and VSS1 as possible. * Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1', L2 = L2'). * Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel. * Capacitance of C2 must be more than 0.1F. * Use thicker pattern for VDD1 and VSS1.
L2 L1 VSS1 C1 C2
VDD1 L1'
L2'
VDD3, VSS3 Terminal Condition
It is necessary to place capacitors between VDD3 and VSS3 as describe below. * Place capacitors as close to VDD3 and VSS3 as possible. * Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L3 = L3'). * Capacitance of C3 must be more than 0.1F. * Use thicker pattern for VDD3 and VDD3.
L3 VSS3 C3
VDD3 L3'
No.A0664-24/28
LC87F5LP6A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 12MHz 10MHz MURATA 8MHz CSTCE12M0G52-R0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 5MHz CSTCR5M00G53-R0 CSTLS5M00G53-B0 (10) (10) (15) (10) (15) (15) (15) C2 [pF] (10) (10) (15) (10) (15) (15) (15) Rf1 [] Open Open Open Open Open Open Open Rd1 [] 470 1.0k 680 2.2k 680 3.3k 1.5k Operating Voltage Range [V] 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 2.5 to 5.5 2.5 to 5.5 Oscillation Stabilization Time typ [ms] 0.05 0.05 0.05 0.05 0.05 0.05 0.05 max [ms] 0.15 0.15 0.15 0.15 0.15 0.15 0.15 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal Frequency Vendor Name SEIKO EPSON Circuit Constant Oscillator Name C3 [pF] 32.768kHz MC-306 18 C4 [pF] 18 Rf2 [] Open Rd2 [] 560k Operating Voltage Range [V] 2.5 to 5.5 Oscillation Stabilization Time typ [s] 1.3 max [s] 3.0 Applicable CL value=12.5pF Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Fig. 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern.
CF1 Rf1
CF2
XT1 Rd1
XT2
Rf2 Rd2
C1
CF
C2
C3 X'tal
C4
Figure 1 Ceramic Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0664-25/28
LC87F5LP6A
VDD Power supply VDD limit GND Reset time RES
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
Operating mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal VALID
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times
No.A0664-26/28
LC87F5LP6A
VDD
RRES
RES CRES
Note: Select CRES and RRES value to assure that at least 200s reset time is generated after the VDD becomes higher than the minimum operating voltage.
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transmission period (SIO0, 2 only)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transmission period (SIO0, 2 only) tSCKLA SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 6 Serial I/O Test Condition
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0664-27/28
LC87F5LP6A
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This catalog provides information as of March, 2007. Specifications and information herein are subject to change without notice.
PS No.A0664-28/28

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